R03: Garbling Gadgets for Boolean and Arithmetic Circuits
Arithmetic garbling provides free additions and specialized gadgets, with a stated symmetric-primitive security model. PLLM status: PLLM component adaptation.
Status: PLLM component adaptation
Year: 2016
Authors: Marshall Ball, Tal Malkin, Mike Rosulek
External source: Garbling Gadgets for Boolean and Arithmetic Circuits
Source contribution
Arithmetic garbling provides free additions and specialized gadgets, with a stated symmetric-primitive security model.
PLLM perspective
Create a reviewed arithmetic-label core with modulus-specific offsets, permitted constant operations, projection and mixed-modulus gadgets. Keep offsets opaque.
Affine-label arithmetic exists in archived references; no proof-equivalent native port has been established.
PLLM uses the source-locked projection and CRT constructions in a clean-room compact Q7 implementation beside a retained dense-table baseline. A separate scheduler supports at most four independent lanes. This is a scoped component adaptation, not a paper reproduction, reviewed protected runtime, real-model tensor method, or complete-model result.
The source's boundary remains binding: Functionality alone does not validate affine-label correlations or an arbitrary hash replacement. Reject unsupported non-unit constants or lower them through justified gadgets.
PLLM modules and documentation
Target module identifiers: garble.arithmetic, gate.mixed_modulus. These identifiers describe scoped work unless this page explicitly links an implementation source. Dependencies: None.
- Research backlog
- Reimplementation backlog
- Clean-room workflow
- Arithmetic garbling documentation
- Reference garbling source
Backlog
This source is assigned to reimplementation priority 3, Arithmetic garbling foundation. Its source-registry order is 3. Follow current gates and unfinished work in the research backlog.
R02: ReDASH: Fast and efficient Scaling in Arithmetic Garbled Circuits for Secure Outsourced Inference
ReDASH generalizes residue-number-system scaling and uses ScaleQuant+ to reduce encoded-inference overhead. PLLM status: reference primitive only.
R04: Two Halves Make a Whole: Reducing Data Transfer in Garbled Circuits using Half Gates
Half-gates reduce AND-gate communication while remaining compatible with free XOR. PLLM status: tracked.