pllm
SDK
ProtocolsGarbling

Half-gates

Boolean AND-gate representation and the obligations surrounding free-XOR circuit execution.

PLLM documentationView Markdown ↗

Half-gates reduce encrypted table material for Boolean AND gates under compatible label and hash assumptions. A component contract must bind circuit identity, wire labels, correlation assumptions, evaluator material, one-time use, serialization, and output decoding.

The topology and gate equations come from Two Halves Make a Whole; any PLLM backend must remain an independently written, bounded implementation.

PLLM documents this category for composition and research mapping. Presence in the taxonomy does not state that a reviewed native implementation or executable profile exists.

No public Python API currently exposes a half-gate component. See research evidence for the evidence boundary; taxonomy alone does not provide executable SDK support.

Loading documentation index…

Search runs locally in this browser.